1. Technical Field
The invention relates to a digital/analog converter with thermometer code driving for converting a binary coded data word into an analog output signal.
2. Related Art
A digital/analog converter converts a digital value into a voltage proportional thereto. In many digital/analog converters, the conversion of a digital value into a voltage proportional thereto is effected by summation and currents which are generated by current sources.
Whereas digital/analog converters which use current sources for generating the analog output voltage operate with a thermometer code, in digital/analog converters which use capacitor networks or a capacitor matrix for quantizing the analog value, binary coded control signals are used for driving the capacitor network. The reason for this is that, given a data word width n of the digital value D to be converted, 2n capacitors have to be driven when thermometer-coded control signals are used, whereas only n capacitors have to be driven in the case of binary-thermometer-coded control signals. The 2n capacitors of a capacitor network which is driven with thermometer-coded control signals are driven by a corresponding number of control lines. The control lines are capacitively coupled to one another, with the result that the capacitances of the capacitors within the capacitor network are altered by the coupling capacitance on the control lines and, consequently, the voltage result is corrupted. The higher the number of required control lines, the greater are the parasitic coupling capacitances between the control lines and the associated signal corruptions on the output signal of the digital/analog converter. Digital/analog converters which use binary for driving the capacitor network have the disadvantage, however, that the differential nonlinearity DNL and the characteristic curve deviations TUE from the ideal stepped converter curve of the digital/analog converter are relatively high on account of matching errors or deviations in the capacitance of the fabricated capacitors from the ideally prescribed capacitance.
FIG. 1a shows the deviation of the characteristic curve from the ideal stepped converter characteristic curve in the case of a conventional 8-bit digital/analog converter, the characteristic curve deviation TUE (Total Unadjusted Error) being normalized to the least significant bit LSB of the digital value to be converted.
FIG. 1b shows the associated differential nonlinearity DNL of a conventional digital/analog converter.
As can be gathered from FIGS. 1a, 1b, a major deviation from the ideal converter characteristic curve occurs in the middle of the converter characteristic curve of the conventional digital/analog converter with capacitance network which is driven with binary coded control signals. In the case of the 8-bit digital/analog converter, at the transition from the digital value 127 (0111111) to the digital value 128 (1000000), the capacitor having the largest capacitance, which corresponds to the sum of all the other capacitances, is connected in, while the remaining capacitors having low capacitances are disconnected, with the result that matching errors have a pronounced effect.
The object of the present invention, therefore, is to provide a digital/analog converter which has a minimal differential nonlinearity DNL.
This object is achieved according to the invention by means of a digital/analog converter having the features specified in patent claim 1.
The invention provides a digital/analog converter for converting a binary coded data word into an analog output signal, having: a capacitor cell matrix comprising capacitor cells which are arranged in matrix form in columns and rows and are driven by thermometer-coded control signals via control lines, a first coding device for recoding the n more significant data bits of the data word to be converted into a thermometer-coded column control signal which has a width of 2n bite and is applied to the capacitor cell matrix via column control lines, a second coding device for recoding the m less significant data bits of the data word to be converted into a thermometer-coded row control signal which has a width of 2m bits and is applied to the capacitor cell matrix via row control lines, each capacitor cell in each case having an associated local decoding circuit which drives switches of the capacitor cell, in a manner dependent on the thermometer-coded row control signal and the thermometer-coded column control signal, which switches through-connect at least one capacitor contained in the capacitor cell to different reference voltages.
Through the use of thermometer-coded control signals, the capacitors of the capacitor cell matrix are driven linearly, i.e. an additional capacitor cell of the capacitor cell matrix is activated at the transition from one digital value to the next digital value.
The local decoding circuit of the capacitor cell arranged in the i-th column and the j-th row preferably has a first logic circuit for logic NAND combination of the signal present on the i-th column control line and the signal present on the j-th row control line, a second logic circuit for logic inversion of the signal present on the i-1-th column control line, and a third logic circuit for logic NAND combination of the first logic circuit and the second logic circuit to form a local control signal for the switches contained in the capacitor cell.
The capacitor cells of the capacitor tell matrix are preferably of differential construction.
In this case, each capacitor cell preferably has two capacitors having the same capacitance, which can be respectively Connected via two associated switches to a positive reference voltage or a negative reference voltage.
The local decoding circuit of a capacitor cell is preferably likewise of differential construction.
In this case, the differentially constructed local decoding circuit preferably contains a first decoding device, which drives the switches of the first capacitor of the differentially constructed capacitor cell in a manner dependent on the thermometer-coded control signals present, and a second decoding device, which drive the switches of the second capacitor of the differentially constructed capacitor cell in a manner dependent on the inverted thermometer-coded control signals present.
The control lines are preferably likewise routed differentially, i.e. when a control line undergoes transition from a logic low value to a logic high value, the adjacent control line undergoes transition from a logic high value to a logic low value.
This affords the particular advantage that instances of capacitive coupling-in on account of coupling capacitances between the control lines are compensated.
The two capacitors of the differentially constructed capacitor cell in each case have a first terminal, which is connected to two controllable switches, for connection of the compacitor to a positive and a negative reference voltage, and a second terminal, which is connected to a common potential node of all the capacitor cells.
The common potential node is preferably connected to a signal output of the digital/analog converter for outputting the analog output signal.
The local decoding circuit is preferably supplied with a supply voltage via a signal level converter circuit for increasing the voltage swing at the capacitors.
The logic circuits of the local decoding circuit are preferably constructed using MOSFET transistors.
The switches of the capacitor cells are preferably likewise MOSFET transistors.
The capacitor cells are preferably fabricated using CMOS technology.
In a particularly preferred embodiment, the capacitor cells are of multilayer construction, the control lines and the local decoding circuit of a capacitor cell being arranged below the associated capacitors of the capacitor cell.
In a particular preferred embodiment, the differentially constructed capacitor cells of the capacitor cell matrix are of multilayer construction with five metal layers, the local decoding circuits being arranged below the firs; metal layer in a semiconductor substrate, the row control lines being formed by the first metal layer, the column control lines being formed by the second metal layer, the first capacitors of the capacitor cells being formed by a dielectric located between the third and fourth metal layers, and the second capacitors of the capacitor cells being formed by a dielectric located between the fourth and fifth metal layers.
The multilayer construction of the capacitor cells leads to a considerable saving of area when the digital/analog converter according to the invention is integrated on a chip, and thus to a considerable reduction in the fabrication costs